POWER MANAGEMENT IN CPU DESIGN

INTRODUCTION

Why power is important:,

Notebook Computers (Like Poly's!)

Server Farms

Embedded Applications

The power used by a computer depends on many factors besides the CPU. Nevertheless we will focus on that. See Figure 1.

THEORY

Three CMOS Power Equations [TNM]

Power = Dynamic Power + Short Circuit Power + Leakage Power

The equation consists of three terms.

1. Dynamic Power to Charge Capacitors:

The first estimates the dynamic power consumed by charging and discharging the capacitance at each gates output. A is the activity (the fraction of the gates switching each clock). C is the total capacitance driven by all the gates outputs. V is the operating voltage. f is the frequency of the clock.

2. Short Circuit Power:

The second term estimates the power expended by the "short-circuit" current which momentarily flows between the supply voltage and ground when the CMOS gates switch. estimates the duration of the flow, and Ishort the amount of current.

3. Leakage Power

Finally, the third term estimates the power due to current leakage:

Ileak estimates this current.

Today, in practice, the first term dominates. Since voltage enters quadratically, it would seem that reducing voltage would be the most attractive means of reducing power expenditure. However, this reduces performance because the device would now find it more difficult (more specifically it would take more time) to recognize the correct state represented by a changing voltage. This limits the operating frequency.

This leads to the second equation (estimate):

where we see that we have to reduce the threshold voltage. But this has consequences as well, in that this increase the leakage power as seen in the third and final equation:

where T is temperature and q and k are physical constants. Thus, if we decrease voltage too much the third, leakage, term in the power equation may become significant. Nevertheless, reducing voltage is a worthwhile approach is being followed. Still the increase in power is frightening. The following data on Alphas illustrate this (http://bwrc.eecs.berkeley.edu/CIC/summary/local/summary.pdf via [TNM].)

Other Measures Related to Power [TNM]

The power equation just introduced gives an average power, put physical damage may depend more on peak power loads. Erratic and sharp changes in power loads may lead to circuit malfunctions. Note also that if we're concerned about battery operation, the storage capability of batteries is measured by energy which is the time integral of power.

Power and Chips:

Integrated circuit technology is characterized by the "feature size" used. Current technology is 0.18 micron (10-6 meters), down from 10 microns in 1971. Intel is now using 90nm. technology. The feature size determines the minimum dimension of a wire or transistor. Thus for a given size chip, the density of transistors can grow quadratically. However, as the feature size decreases the voltage used must decrease as well. This might seem to reduce power consumption, but other factors are at work, and net power use actually increases dramatically over the generations of chip technology. Because the number of transistors is growing roughly quadratically, and the clock rates are increasing, more transisters must be switched more frequently causing a net increase in power use. High performance workstations and server processors use between 100 and 159 watts. Moreover, since the wires are generally smaller so the resistance increases and closer together so that the capacitance increases increasing the RC time delay in transmission.

The following table from {TNM] illustrates both the increase in power used in successive generations of the HP Alpha cpu's:

Alpha Model Peak Power (W) Frequency (Mhz) Die size (mm.2) Supply Voltage
21064 30 200 234 3.3
21164 50 300 299 3.3
21264 72 667 302 2.0
21364 100 1,000 350 1.5
21464 125-150 1000-2000 350 1.2

[TNM]

The last processor was probably the last Alpha designed since Compaq canceled the project before any deliveries.. The design team is reported to be working, intact, for Intel (which manufactured the Alpha in recent years) on the IA64 [Paul DeMone http://www.realworldtech.com/ 2/02].

One factor that is very important in power usage is memory, especially for imbedded processors.

If a computer is "in standby or low power mode" for long lengths of time, the power required to refresh DRAM is significant; perhaps, making SRAM more attractive.

Caches, especially on chip, also save power because less power is required to get information from on-chip cache then to go to an external bus and memory.

HOW TO REDUCE POWER

Shut off or slow down processor when not being (heavily) used:

Most directly, you can "suspend," or "put to sleep" a processor when it isn't being used (e.g., your notebooks). This essentially means if the CPU is not doing useful work save the program state to RAM, or more "deeply" to disk and shut the CPU "down."

Generally speaking the more power you save the longer the latency to return to full performance. Note that O/S support is needed for many of these schemes.

Intel mobile chips can reduce the clock by 100 Hz when not plugged in; Transmeta LongRun reduces clock and voltage on the fly depending on the load. [Stokes]

Reduce voltage:

The first, and currently most important term in the power equation depends on V2 so it is attractive to try to save power by reducing voltage. As the feature size goes down the voltage needs to be decreased in any case. The Alpha table shows this. Processors such as the Transmneta Crusoe can reduce voltage on the fly. The M-CORE of Moterola reduces the leakage term by reducing the voltage drop in "low performance" parts of the chip.

Reduce Power Used in Clocking:

Clock signal distribution in processors can take up about 30% of total power expended in a processor. This makes a tempting target for power saving. You can turn off the clock in parts of the processor where and when it is not being used (gated clocking). This not only saves clock power but also the logic which is switched. Instead of clocking on, say only, the rising edge of the clock pulse you can halve the frequency and trigger on rising and falling edges (DDR memory). Even more effectively, you can reduce the voltage swing of the clock signal ( "half swing clocks"). Finally, you can slow down the clock when you don't need all the capability of the processor (Transmeta Crusoe). Or you can do away with a clock, at least in part, by using asynchronous computing in portions of the device where you can organize logic without using a clock.

An Example of a Low Power Design: The Transmeta Crusoe

The Crusoe is VLIW processor (like the Itanium) designed for the low-power market place, especially mobile PCs and mobile Internet appliances. Provides ISA compatibility with Intel x86 by translating (using relatively fancy techniques which they call Software Morphing--it is very close to emulation) Cisc instructions into Crusoe VLIW instructions.

AMD 700 Mhz K7 (0.18 micron technology) consumes 34 watts. An Intel 0.18 micron mobile penium III at 400MHz uses approximately 7.5 watts. 700MHz Crusoe (0.18 micron) uses 1 watt [Stokes] (Note, however, that the Crusoe has a lot of extra functions in software that the AMD does in hardware!) If not much is going on LongRun can be used to reduce the power consumed to as low as 10-20mw [http://www.sharkyextreme.com/hardware/articles/transmeta_crusoe/

LongRun®


LongRun is a power management technique developed by Transmeta. LongRun works by monitoring the precise performance level needed by an application, and then dynamically adjusting the Crusoe processor's operating speed and voltage to match that need. With LongRun, Crusoe can make adjustments while the application is running, thereby making the most efficient use of power, for the longest battery life. (From Transmeta).

Intel, AMD, IBM

Intel SpeedStep technology reduces voltage and frequency when a portable is battary power, and increases it when running form external power.

AMD features PowerNow, which can dynamically change operationg voltage and frequency based on demand.

IBM has announced PowerPC 405LP with a "ultra-low-power-operation" for use in portable devices where the voltage and clock frequency can be modified on the fly as the needs of applications change. (Gary H. Anthes, ComputerWorld, 9/2/2002.)

SOURCES:

Hennessy, John and David Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., Morgan-Kaufmann, 2003, pp. xviii, 7, 8,13-14, 56-57, 369-370, 457, 480.

Mudge, Trevor, POWER: A First-Class Architectural Design Constraint, IEEE Computer Magazine, pp. 52-58, April, 2001. ( = [TNM])

Stokes, Jon, "Crusoe Explored," http://www.arstechnica.com/cpu/1q00/crusoe/crusoe-1.html

R. Van Slyke January 15, 2003