This article provides a synopsis from the Intel technical books on the operation of dual Pentium CPUs.

Some models of Intel’s Pentium processor series incorporate a private CPU-CPU bus arbitration protocol that enables two processors to content for bus control, without the use of an external bus controller.  This bus arbitration scheme is designed to efficiently use bus bandwidth, provide fair access, support inter-CPU pipe-lining, and not introduce dead-lock with dual processors [PPFDM, vol 1, page 20-3].

During system initialization (i.e., system reset), the CPU in socket 7 checks for a processor in socket 5, and then performs a boot sequence. This initially places the CPU in socket 7 as the primary processor (MRM) and the CPU in socket 5 as the dual processor (LRM). In spite of their names, the CPUs have symmetric processing power, access to memory, cache, and the system buses.
 

Access to the system buses (data, address, and control) are negotiated through the bi-directional control lines: PBREQ# and PBGNT#, Private Bus REQuest, and Private Bus GraNT, respectively.  The CPUs “toggle” between being in MRM and LRM modes, with the MRM being in “control” of the system bus.  Operationally, the current MRM has exclusive access to the system’s buses, and the LRM must request ownership via the assertion of the its PBREQ# pin. When the MRM completes its current cycle, it gives ownership of the buses to the LRM by asserting the BPGNT# pin. This then reverses each processor’s role, that is, the MRM becomes the LRM, and the converse, the LRM becomes the MRM. 

Note that the bi-directional semantics of the PBREQ# and PBGNT# pins reduce the number of required pins. 

There are other aspects that are beyond the scope of this introuction such as how the processors take into account the current state of the system bus and the cache.