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Patrick Crowley
Washington University in St. Louis
Tuesday, Oct. 25, 11:00am
LC 400, Brooklyn Campus, Polytechnic University
Abstract
While general-purpose processors have only recently employed chip
multiprocessor (CMP) architectures, network processors (NPs) have used
heterogeneous multi-core architectures since the late 1990s. NPs differ
qualitatively from workstation and server CMPs in that they replicate
many simple, highly efficient processor cores on a chip, rather than a
small number of sophisticated superscalar CPUs. In this talk, we compare
the performance of one such NP, the Intel IXP 2850, to that of the Intel
Pentium 4 when executing a scientific computing workload with a high
degree of thread-level parallelism. Our target program, HMMer, is a
bioinformatics tool that identifies conserved motifs in protein
sequences. HMMer represents motifs as hidden Markov models (HMMs) and
spends most of its time executing the well-known Viterbi algorithm to
align proteins to these models. Our observations of HMMer on the IXP are
therefore relevant to computations in many other domains that rely on
the Viterbi algorithm. We show that the IXP achieves a speedup of 1.82
over the Pentium, despite the Pentium's 1.85x faster clock. Moreover, we
argue that next-generation IXP NPs will likely provide a 10-20x speedup
for our workload over the IXP 2850, in contrast to 5-10x speedup
expected from a next-generation Pentium-based CMP.
Bio
Patrick Crowley is assistant professor in the Department of Computer
Science and Engineering at Washington University in St. Louis, where he
is a member of the Applied Research Laboratory. Crowley's current work
has three main areas: A) the design and application of multi-core
processors for networking and other areas such as computational biology
and scalable virtual machine implementations, B) the design of a
storage-based supercomputer-class system that exploits advanced FPGAs
and multi-core processors to scale scientific compute throughput with
the rate of data transfer off a local disk, and C) high-performance router
architectures, with a particular emphasis on the design of diversified
routers capable of supporting multiple coexisting network architectures
on a single provisioned physical substrate. Crowley is co-editor of the
three-book series "Network Processor Design" and co-founder of the ACM/IEEE
Symposium on Architectures for Networking and Communications Systems (ANCS),
the first of which will be held in Princeton, N.J. in October 2005. More
information is available on his
homepage.
For further information please contact Haldun Hadimioglu (haldun at photon.poly.edu)